Download An Artificial Intelligence Approach to VLSI Routing by R. Joobbani PDF

By R. Joobbani

Routing of VLSI chips is a vital, time eating, and hard challenge. the trouble of the matter is attributed to the big variety of frequently conflicting elements that impact the routing caliber. conventional concepts have approached routing by means of ignoring a few of these elements and enforcing pointless constraints for you to make routing tractable. as well as the imposition of those regulations, which simplify the issues to a point yet even as lessen the routing caliber, conventional methods use brute strength. they typically remodel the matter into mathematical or graph difficulties and fully forget about the categorical wisdom concerning the routing activity which can tremendously aid the answer. This thesis overcomes the various above difficulties and provides a method that plays routing with reference to what human designers do. In different phrases it seriously capitalizes at the wisdom of human services during this region, it doesn't impose pointless constraints, it considers the entire various factors that impact the routing caliber, and most significantly it permits consistent person interplay in the course of the routing procedure. to accomplish the above, this thesis provides heritage approximately a few consultant concepts for routing and summarizes their features. It then reviews intimately the various elements (such as minimal quarter, variety of vias, twine size, etc.) that have an effect on the routing caliber, and the various standards (such as vertical/horizontal constraint graph, merging, minimum rectilinear Steiner tree, etc.) that may be used to optimize those factors.

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Consequently, after the first step there are only 4 sets of nets remaining to be merged further (1-3, 4, 5 and 6-8). i-6-7 1 - 3 - 1 -5 - § - 8 2-1-5-6-7 2-4-6-11-8 (al Figu re 3·15: Comparison of two merging techniques. (a) merging proceeds from left to right, (b) merging proceeds from left and right to the center. The effectiveness of this approach can be seen in real examples where the number of cases without employing these two techniques is staggering and impossible to consider. 5. Vertical/horizontal constraint graph The vertical constraint graph was described in Chapter 2.

Eliminate all the nodes with one edge as described in the second reduction rule. 5. Exhaustively generate the trees for the remaining nodes [Mcilroy 69, Minty 65] and choose the shortest tree. 6. The union of the edges eliminated in step 4 and the edges of the shortest tree in step 5 is the desired MRST. Figure 3-12 shows the step by step calculation of the optimal rectilinear Steiner tree for the example of Figure 3-12(a). 1 (a) a b e bad9 f I: d d· :1 9 e h f e f (e) (d) C (e) (b) h MRST ={ El a } (f) Assuming e > b MRST • { + C a.

Hardware: Hardware effort has concentrated on machines that can execute symbolic manipulation languages, such as LISP and PROLOG, more effiCiently. Examples of these machines include: the Xerox D series machine effort [Xerox 84], the LISP machine from Symbolics [Symbolics 84], the LISP machine from Lisp Machine Incorporated (lMI) [lMI 84], the Explorer from Texas Instrument [TI 84], and the Japanese Prolog Sequential Inference Machine [Murtha 85]. Another effort has been directed in packaging of traditional CPUs, such as the Motorola 68000 [MC68000 82] series, with appropriate hardware and software.

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